The present invention relates to memory devices and methods of testing thereof, and more particularly, to memory devices having an internal circuit for improving test efficiency and a method of testing thereof.
In general, semiconductor memory devices are tested before sale to users. The time taken to perform tests can cause an increase in the cost of the product. Therefore, many efforts have been made to shorten the time needed for testing. As it can be difficult to reduce the number of items tested in a memory device, a plurality of devices are typically tested in parallel to reduce the total time needed for testing. As a result, the time necessary for testing can be reduced in proportion to the number of products that can be simultaneously tested by a testing instrument.
A typical semiconductor memory device includes a plurality of data input/output pins for inputting/outputting binary data and a plurality of control pins for controlling the semiconductor memory device. When testing such a semiconductor memory device, the control and input/output pins of the test instrument typically are connected to data input/output pins and control pins of the semiconductor memory device. When multiple devices are tested in parallel, a control signal may be applied to the control pins of multiple devices.
However, a data output signal of the semiconductor memory device may vary depending on the product. Conventionally, this may mean that all of the data input/output pins of each product to be tested are required to be connected to input/output pins of the testing instrument in a one-to-one relationship. Therefore, the number of simultaneously testable products is typically determined according to the number of data input/output pins of each product.
Semiconductor memory devices can be classified, for example, as X4 products, X8 products or X16 products based on the amount of binary data that can be input/output at a time. A X4 product includes four data input/output pins to process four data bits at a time. An X8 product includes eight data input/output pins to process eight data bits at a time. An X16 product includes sixteen data input/output pins to process sixteen data bits at a time. The number of data input/output pins of an X16 product is double the number of data input/output pins of an X8 product and, therefore, the number of X16 products that are simultaneously testable in a given testing instrument may be half the number of X8 products can be simultaneously tested in the testing instrument.
FIG. 1 shows a X16 semiconductor memory device connected to a testing instrument. In particular, FIG. 1 is a block diagram showing connections of conventional DDR SDRAMs 10 (double data rate synchronous DRAM) to a DRAM testing instrument 20. Control signal input pins 11 of the X16 DDR SDRAMs 10 are connected to control signal output pins 21 of the DRAM testing instrument 20. Data input/output pins 12 of the X16 DDR SDRAMs 10 are similarly connected to data input/output pins 22 of the DRAM testing instrument 20 in a one-to-one fashion. The X16 DDR SDRAMs 10 output data to or input data from the data input/output pins 22 of the DRAM testing instrument 20 through the data input/output pins 12 based on a control signal output from the DRAM testing instrument 20. The DRAM testing instrument 20 checks data input to the data input/output pins 22 and received from the data input/output pins 22 to verify whether the DDR SDRAMs are faulty. Because the data input/output pins 12 of the X16 DDR SDRAM are connected to the data input/output pins 22 of the DRAM testing instrument 20 in a one-to-one relationship, the number of X16 DDR SDRAM that be simultaneously tested is considerably limited in comparison to the number of the X8 DDR SDRAM that can be simultaneously tested.
FIG. 2 is a block diagram of an internal circuit of a DDR SDRAM such as those shown in the FIG. 1. An internal circuit 30 of the DDR SDRAM includes an internal circuit decision unit 31, a command decoder 32, a control signal generator 33, a first input buffer 34, a second input buffer 35, a DQ (data input/output) buffer controller 36, a first write controller 37, a second write controller 38, a plurality of DQ buffers 39, and a plurality of drivers 40. The internal circuit decision unit 31 outputs a control signal PINOUT and determines a number of input/output data pins of the DDR SDRAM and the internal circuit corresponding thereto. The command decoder 32 outputs a plurality of control commands in response to externally input control signals C0, C1, . . . , CX. The control signal generator 33 activates a control signal PBUFEN (not shown) in response to a data write command WRITE output from the command decoder 32 and outputs the activated control signal PBUFEN.
The control signal PBUFEN causes the first input buffer 34 and the second input buffer 35 to turn on or off. The first input buffer 34 and the second input buffer 35 are turned on as the control signal PBUFEN is activated. The first input buffer 34 and the second input buffer 35 activate control signals UDMT and LDMT respectively, in response to input external write inhibit signals UDM and LDM. The first write controller 37 and the second write controller 38 operate based on the control signals UDMT and LDMT.
The first write controller 37 and the second write controller 38 control write operations for data input to the eight data input/output pins 12. More specifically, when the control signal UDMT is in a de-asserted state, the first write controller 37 prevents data present at the eight data input/output pins 12, which are controlled by the first write controller 37, from being written in a memory cell (not shown). When the control signal LDMT is in a de-asserted state, the second write controller 38 prevent data at the eight data input/output pins 12, which are controlled by the second write controller 38, from being written in the memory cell.
The first input buffer 34, the second input buffer 35, the first write controller 37, the second write controller 38, and the control signal generator 33 are not used in a test mode of the DDR SDRAM, but are used in a data write operation of the DDR SDRAM. The DQ buffer controller 36 outputs a control signal PTRST in response to a data read command signal READ that is output from the command decoder 32. The control signal PTRST is asserted in response to the data read command signal READ and is then de-asserted after a predetermined time. If the control signal PTRST is asserted, data is output from the data input/output pins 12.
The DQ buffers 39 are connected to the data input/output pins 12 via the drivers 40. All of the DQ buffers 39 are turned on or off according to the control signal PINOUT. If the control signal PTRST is asserted, the plurality of DQ buffers 39 generate internal signals by synchronizing data in a memory cell, i.e., the data produced DO0, DO1, DO2, . . . , DO15 on internal data lines 14, to external clock signals. The plurality of drivers 40 receive the internal signals and output them as data, i.e., DQ0, DQ1, DQ2, . . . , DQ15, via the data input/output pins 12. If the control signal PTRST is de-asserted, the DQ buffers 39 and the drivers 40 transition to a high impedance state, and as a result, data DQ0, DQ1, DQ2, . . . , DQ15 is not output. In order to output the data, DO0, DO1, DO2, . . . , DO15, at a high speed to a large external load capacitance, the plurality of drivers 40 provide an increased current sourcing/sinking capabilities for data pins 12. The plurality of drivers 40 output the data, DO0, DO1, . . . , DO15, as the data, DQ0, DQ1, DQ2, . . . , DQ15, via the data input/output pins 12.
FIG. 3 is a timing chart showing signals of the DDR SDRAM shown in FIG. 2 in a test mode of the DDR SDRAM. In the test mode, if the command decoder 32 outputs a data read command signal READ in synchronization with a clock signal CLK, the DQ buffer controller 36 responds to the data read command signal READ and asserts the control signal PTRST. As the control signal PTRST is asserted, the DQ buffers 39 are turned on to activate the drivers 40, and data, DQ0, DQ1, DQ2, . . . , DQ15, are output through the drivers 40. Because the control signal generator 33, the first input buffer 34 and the second input buffer 35 are not used in the test mode of the DDR SDRAM, the control signal PBUFEN is in a deactivated state. In addition, because the write inhibit signals UDM and LDM are not activated, the control signals UDMT and LDMT are also not activated.
As described above, because the data input/output pins of the conventional DDR SDRAM are typically connected to the data input/output pins of the testing instrument in a one-to-one relationship, the number of products that are simultaneously testable can be limited. Therefore, there exists a need for reducing the number of data input/output pins of a semiconductor memory device used in testing, in order to increase the number of semiconductor memory devices that can be simultaneously tested with a single testing instrument.